Conventionally, a data cache memory (DATA-RAM) protects data by appending an Error-Check-and-Correction (ECC) byte to an 8-byte data. An ECC is stored in an ECC cache memory (ECC-RAM) that is separate from DATA-RAM, and dedicatedly provided for ECCs. The ECC-RAM is updated when a register or a write operation is performed to the cache memory.
A common method of generating an ECC will now be explained with reference to FIG. 17. As depicted FIG. 17, to write data into a cache memory, an instruction processor issues a store instruction to a memory processor. Upon receiving the instruction, the memory processor checks if the cache line to be stored is in the cache memory, and at the same time, reads the data in the cache line to be stored from the cache memory and checks the data for an error. At this time, store data issued from an execution unit and alike is written in a store buffer (STB).
When the instruction processor issues a store permission subsequently, the memory processor writes the data taken out from the store buffer into a write buffer (WB), and further writes the data taken out from the write buffer into the DATA-RAM. At the same time as writing the data, the memory processor generates an ECC based on 8-byte fetched data read from the DATA-RAM, using bytes-not-to-be-stored included therein (ECC generation 1). In addition, the memory processor generates an ECC based on data in the bytes-to-be-stored included in the 8-byte store data (ECC generation 2). The memory processor then merges these two ECCs to generate an ECC corresponding to the updated store data, and stores the generated ECC in the ECC-RAM.
However, a 1-bit error might be different in each of these scenarios, that is, in the data read from the DATA-RAM upon checking for an error when the retrieval access is made to the cache memory in response to the store request; and in the data read therefrom upon generating the ECC after the storing is permitted, and the cache memory is accessed for the write. In other words, if no error is detected at the error check performed upon the data retrieval, but an error is found in the data read upon execution of the write, the ECC corresponding to the data after the write cannot be generated properly. Furthermore, the ECC remaining at this point is one corresponding to the data before the write, and the data before the write has been already lost. Therefore, it is impossible to correct the faulty bit, further making it impossible to correct the 1-bit error upon reading the data before executing the write. The reason why such an uncorrectable error occurs is that, because the data is read from the DATA-RAM twice, the result of each of the reads might be different.
In response to such an issue, a disclosed technique executes an error check and an ECC generation based on a single read (see FIG. 18). In other words, the disclosed memory processor does not use the data read from DATA-RAM upon executing the write. More specifically, an ECC is generated based on the data stored previously, and the ECC is appended to the store data written in the STB, to generate new store data (see Japanese Laid-open Patent Publication No. 01-185753, Japanese Laid-open Patent Publication No. 03-108041, Japanese Laid-open Patent Publication No. 10-232789, and Japanese National Publication of International Patent Publication No. 2004-514184, for example).
However, these conventional techniques have a problem that, when data of equal to or less than 8 bytes are stored in the same address consecutively, Store-Store-Interlock (SSI) may occur, resulting in performance deterioration. More specifically, because a memory processor with such a structure maintains data-not-to-be-stored as an ECC, if the next store instruction executes a write in the same area as the preceding store instruction, the memory processor has to wait for the preceding storing to complete before generating an ECC. Therefore, the memory processor results in detecting SSI for store data other than 8-byte full-store data, thus fails to execute the next storing.